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hsmp-389x series, hsmp-489x series surface mount rf pin switch diodes data sheet features ? unique confgurations in surface mount packages C add flexibility C save board space C reduce cost ? switching C low capacitance C low resistance at low current ? low failure in time (fit) rate [1] ? matched diodes for consistent performance ? better thermal conductivity for higher power dissipation ? lead-free note: 1. for more information see the surface mount pin reliability data sheet. description/applications the hsmp-389x series is optimized for switching appli - cations where low resistance at low current and low ca - pacitance are required. the hsmp-489x series products feature ultra low parasitic inductance. these products are specifcally designed for use at frequencies which are much higher than the upper limit for conventional pin diodes. pin connections and package marking notes: 1. package marking provides orientation, identifcation, and date code. 2. see electrical specifcations for appropriate package marking. gux 1 2 3 6 5 4
2 package lead code identifcation, sot-23/143 (top view) package lead code identifcation, sot-323 (top view) package lead code identifcation, sot-363 (top view) absolute maximum ratings [1] t c = +25c symbol parameter unit sot-23/143 sot-323/363 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v 100 100 t j junction temperature c 150 150 t stg storage temperature c -65 to 150 -65 to 150 jc thermal resistance [2] c/w 500 150 esd warning: handling precautions should be taken to avoid static discharge. notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25c, where t c is defned to be the temperature at the package pins where contact is made to the circuit board. s e r i e s ? s h u n t p a i r l o w i n d u c t a n c e s i n g l e t u n c o n n e c t e d t r i o l 1 2 3 6 5 4 1 2 3 6 5 4 1 2 3 6 5 4 u h i g h f r e q u e n c y s e r i e s v 1 2 3 6 5 4 d u a l s w i t c h m o d e l r 1 2 3 6 5 4 c o m m o n c a t h o d e f c o m m o n a n o d e e s e r i e s c s i n g l e b d u a l a n o d e 4 8 9 b c o m m o n c a t h o d e # 4 c o m m o n a n o d e # 3 s e r i e s # 2 s i n g l e # 0 u n c o n n e c t e d p a i r # 5 d u a l a n o d e 4 8 9 0 r i n g q u a d # 7 1 3 2 4 u n d e r d e v e l o p m e n t
3 electrical specifcations, t c = 25c, each diode package minimum maximum maximum part number marking lead breakdown series resistance total capacitance hsmp- code code confguration voltage v br (v) r s (y) c t (pf) 3890 g0 [1] 0 single 100 2.5 0.30 3892 g2 [1] 2 series 3893 g3 [1] 3 common anode 3894 g4 [1] 4 common cathode 3895 g5 [1] 5 unconnected pair 389b g0 [2] b single 389c g2 [2] c series 389e g3 [2] e common anode 389f g4 [2] f common cathode 389l gl [2] l unconnected trio 389r s [2] r dual switch mode 389t z [2] t low inductance single 389u gu [2] u series-shunt pair 389v gv [2] v high frequency series pair test conditions v r = v br i f = 5 ma v r = 5 v measure f = 100 mhz f = 1 mhz i r 10 a notes: 1. package marking code is white. 2. package is laser marked. high frequency (low inductance, 500 mhz C 3 ghz) pin diodes minimum maximum typical maximum typical part package breakdown series total total total number marking voltage resistance capacitance capacitance inductance hsmp- code [1] confguration v br (v) r s (y) c t (pf) c t (pf) l t (nh) 489x ga dual anode 100 2.5 0.33 0.375 1.0 test conditions v r = v br i f = 5 ma f = 1 mhz v r = 5 v f=500 mhzC measure v r = 5 v f = 1 mhz 3 ghz i r 10 a note: 1. sot-23 package marking code is white; sot-323 is laser marked. typical parameters at t c = 25c part number series resistance carrier lifetime total capacitance hsmp- r s (y) (ns) c t (pf) 389x 3.8 200 0.20 @ 5v test conditions i f = 1 ma i f = 10 ma f = 100 mhz i r = 6 ma
4 hsmp-389x series typical performance, t c = 25c, each diode typical applications for multiple diode products figure 6. hsmp-389l used in a sp3t switch. figure 7. hsmp-389l unconnected trio used in a dual voltage, high isolation switch. 1 1 2 3 4 0 5 6 b1 b2 b3 2 3 1 1 1 rf in rf out 2 2 3 4 5 6 1 0 0 2 +v ?v ?on? ?off? figure 1. total rf resistance at 25 c vs. forward bias current. 100 10 1 0.1 rf resistance (ohms) i f ? forward bias current (ma) 0.01 0.1 1 1 0 100 120 11 5 11 0 105 100 95 90 85 1 1 0 3 0 i f ? forward bias current (ma) figure 3. 2nd harmonic input intercept point vs. forward bias current. input intercept point (dbm) diode mounted as a series attenuator in a 50 ohm microstrip and tested at 123 mhz 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0 4 8 1 2 1 6 2 0 v r ? reverse voltage (v) total capacitance (pf) 1 mhz 1 ghz figure 2. capacitance vs. reverse voltage. 200 160 120 80 40 0 10 20 15 25 30 t rr ? reverse recovery time (ns) forward current (ma) figure 4. typical reverse recovery time vs. reverse voltage. v r = ?2 v v r = ?5 v v r = ?10 v 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f ? forward current (ma) v f ? forward voltage (v) figure 5. forward current vs. forward voltage. 125 c 25 c ? 50 c
5 typical applications for multiple diode products (continued) figure 11. hsmp-389v series/shunt pair used in a 1.8 ghz transmit/receive switch. figure 10. hsmp-389u series/shunt pair used in a 900 mhz transmit/receive switch. figure 8. hsmp-389l unconnected trio used in a positive voltage, high isolation switch. figure 9. hsmp-389t used in a low inductance shunt mounted switch. rf in rf out 1 +v 0 2 0 +v ?on? ?off? 4 5 6 1 1 1 2 2 3 rf in rf out 4 5 6 1 2 3 4 rcvr xmtr bias ant pa bias hsmp-389u lna 4 rcvr bias xmt r hsmp-389v antenna 4 4 rcvr xmtr bias ant c c
6 typical applications for multiple diode products (continued) rf common rf common rf 1 bias 1 bias bias rf 2 bias 2 figure 12. simple spdt switch, using only positive current. rf common rf 1 rf 2 bias figure 14. switch using both positive and negative bias current. figure 15. very high isolation spdt switch, dual bias. figure 13. high isolation spdt switch, dual bias. rf 2 rf 1 rf common rf 2 rf 1 bias
7 equivalent circuit model hsmp-389x chip* typical applications for hsmp-489x low inductance series microstrip series connection for hsmp-489x series in order to take full advantage of the low inductance of the hsmp -489x series when using them in series ap - plications, both lead 1 and lead 2 should be connected together, as shown in figure 17. co-planar waveguide shunt connection for hsmp-489x series co-planar waveguide, with ground on the top side of the printed circuit board, is shown in figure 20. since it eliminates the need for via holes to ground, it ofers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. a spice model is not available for pin diodes as spice does not provide for a key pin diode characteristic, car - rier lifetime. 1 2 3 figure 16. internal connections. hsmp-489x figure 17. circuit layout. 50 ohm micr ostrip lines p ad connected to gr ound by tw o via holes figure 18. circuit layout. 0.3 nh 0.3 nh 0.3 pf 1.5 nh 1.5 nh figure 19. equivalent circuit. figure 20. circuit layout. co-planar wa veguide gr oundplane center conductor gr oundplane 0.12 pf* * measured at -20 v 0.5 ? r j r s c j r j = 20 ? i 0.9 r t = 0.5 + r j c t = c p + c j i = forwar d bias current in ma * see an1124 f or pac kage models figure 21. equivalent circuit. 0.3 pf 0.75 nh figure 16. internal connections. figure 17. circuit layout. microstrip shunt connections for hsmp-489x series in figure 18, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the hsmp-489x diode are placed across the resulting gap. this forces the 1.5 nh lead inductance of leads 1 and 2 to appear as part of a low pass flter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. the 0.3 nh of shunt inductance external to the diode is cre - ated by the via holes, and is a good estimate for 0.032" thick material. figure 18. circuit layout. figure 19. equivalent circuit. figure 20. circuit layout. figure 21. equivalent circuit.
8 assembly information 0.026 0.075 0.016 0.035 figure 22. pcb pad layout, sot-363. (dimensions in inches). 0.026 0.035 0.07 0.016 figure 23. pcb pad layout, sot-323. (dimensions in inches). 0.037 0.95 0.037 0.95 0.079 2.0 0.031 0.8 dimensions in inches mm 0.035 0.9 sot-23 footprint figure 24. pcb pad layout, sot-23. dimensions in inches mm 0.075 1.9 0.071 1.8 0.112 2.85 0.079 2 0.033 0.85 0.041 1.05 0.108 2.75 0.033 0.85 0.047 1.2 0.031 0.8 0.033 0.85 figure 25. pcb pad layout, sot-143.
9 lead-free refow profle recommendation (ipc/jedec j-std-020c) refow parameter lead-free assembly average ramp-up rate (liquidus temperature (t s(max) to peak) 3c/ second max preheat temperature min (t s(min) ) 150c temperature max (t s(max) ) 200c time (min to max) (t s ) 60-180 seconds ts(max) to tl ramp-up rate 3c/second max time maintained above: temperature (t l ) 217c time (t l ) 60-150 seconds peak temperature (t p ) 260 +0/-5c time within 5 c of actual peak temperature (t p ) 20-40 seconds ramp-down rate 6c/second max time 25 c to peak temperature 8 minutes max note 1: all temperatures refer to topside of the package, measured on the package body surface 2 5 t i m e t e m p e r a t u r e t p t l t p t l t 2 5 c t o p e a k r a m p - u p t s t s m i n r a m p - d o w n p r e h e a t c r i t i c a l z o n e t l t o t p t s m a x figure 26. surface mount assembly profle. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase refow, wave soldering, etc.) cir - cuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot package, will reach solder refow temperatures faster than those with a greater mass. avago technologies diodes have been qualifed to the time-temperature profle shown in figure 26. this profle is representative of an ir refow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. the refow zone briefy elevates the temperature suf - ciently to produce a refow of the solder. the rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to compo - nents due to thermal shock. the maximum temperature in the refow zone (t max ) should not exceed 260c. these parameters are typical for a surface mount assem - bly process for avago technologies diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform refow of solder.
10 e b e 2 e 1 e 1 c e x x x l d a a 1 n o t e s : x x x - p a c k a g e m a r k i n g d r a w i n g s a r e n o t t o s c a l e d i m e n s i o n s ( m m ) m i n . 0 . 7 9 0 . 0 0 0 0 . 3 0 0 . 0 8 2 . 7 3 1 . 1 5 0 . 8 9 1 . 7 8 0 . 4 5 2 . 1 0 0 . 4 5 m a x . 1 . 2 0 0 . 1 0 0 0 . 5 4 0 . 2 0 3 . 1 3 1 . 5 0 1 . 0 2 2 . 0 4 0 . 6 0 2 . 7 0 0 . 6 9 s y m b o l a a 1 b c d e 1 e e 1 e 2 e l e b e2 b1 e1 e1 c e xxx l d a a1 notes: xxx-package marking drawings are not to scale dimensions (mm) min. 0.79 0.013 0.36 0.76 0.086 2.80 1.20 0.89 1.78 0.45 2.10 0.45 max. 1.097 0.10 0.54 0.92 0.152 3.06 1.40 1.02 2.04 0.60 2.65 0.69 symbo l a a1 b b1 c d e1 e e1 e2 e l e b e 1 e 1 c e x x x l d a a 1 n o t e s : x x x - p a c k a g e m a r k i n g d r a w i n g s a r e n o t t o s c a l e d i m e n s i o n s ( m m ) m i n . 0 . 8 0 0 . 0 0 0 . 1 5 0 . 0 8 1 . 8 0 1 . 1 0 1 . 8 0 0 . 2 6 m a x . 1 . 0 0 0 . 1 0 0 . 4 0 0 . 2 5 2 . 2 5 1 . 4 0 2 . 4 0 0 . 4 6 s y m b o l a a 1 b c d e 1 e e 1 e l 1 . 3 0 t y p i c a l 0 . 6 5 t y p i c a l e h e d e a 1 b a a 2 d i m e n s i o n s ( m m ) m i n . 1 . 1 5 1 . 8 0 1 . 8 0 0 . 8 0 0 . 8 0 0 . 0 0 0 . 1 5 0 . 0 8 0 . 1 0 m a x . 1 . 3 5 2 . 2 5 2 . 4 0 1 . 1 0 1 . 0 0 0 . 1 0 0 . 3 0 0 . 2 5 0 . 4 6 s y m b o l e d h e a a 2 a 1 e b c l 0 . 6 5 0 b c s l c package dimensions outline 23 (sot-23) outline 143 (sot-143) outline sot-363 (sc-70 6 lead) outline sot-323 (sc-70 3 lead)
11 user feed direction cover tape carrier tape reel note: "ab" represents package marking code. "c" re p resents date code. end vie w 8 mm 4 mm top view abc abc abc abc note: "ab" represents package marking code. "c" represents date code. end vie w 8 mm 4 mm top view abc abc abc abc end vie w 8 mm 4 mm top view note: "ab" represents package marking code. "c" represents date code. abc abc abc abc option descriptions -blkg = bulk, 100 pcs. per antistatic bag -tr1g = tape and reel, 3000 devices per 7" reel -tr2g = tape and reel, 10,000 devices per 13" reel tape and reeling conforms to electronic industries rs-481, taping of surface mounted components for automated placement. device orientation for outline sot-143 for outlines sot-23, -323 for outline sot-363 ordering information specify part number followed by option. for example: hsmp - 389x - xxx bulk or tape and reel option part number; x = lead code surface mount pin package characteristics lead material copper (sot-323/363); alloy 42 (sot-23/143) lead finish tin 100% maximum soldering temperature 260c for 5 seconds minimum lead strength 2 pounds pull typical package inductance 2 nh typical package capacitance 0.08 pf (opposite leads)
12 tape dimensions and product orientation for outline sot-143 for outline sot-23 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.1 0 2.77 0.1 0 1.22 0.1 0 4.00 0.1 0 1.00 + 0. 05 0.124 0.004 0.109 0.004 0.048 0.00 4 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.1 0 1.75 0.1 0 0.059 + 0.00 4 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 ? 0.10 0.229 0.013 0.315 + 0.012 ? 0.00 4 0.009 0.000 5 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.0 5 2.00 0.0 5 0.138 0.002 0.079 0.002 distance between centerlin e w f e p 2 p 0 d p d 1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.19 0.10 2.80 0.10 1.31 0.10 4.00 0.10 1.00 + 0. 25 0.126 0.004 0.110 0.004 0.052 0.004 0.157 0.004 0.039 + 0. 010 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 ? 0.10 0.254 0.013 0.315+ 0.012 ? 0.004 0.0100 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance a 0 9 max 9 max t 1 b 0 k 0
tape dimensions and product orientation for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. obsoletes 5989-0486en av02-0813en - june 2, 2009 for outlines sot-323, -363 p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness) an b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.254 0.02 0.315 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance for sot-323 (sc70-3 lead) an 8 c max for sot-363 (sc70-6 lead) 10 c max angle width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape

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